Version 4 SHEET 1 1360 3428 WIRE 64 -96 -192 -96 WIRE 208 -96 64 -96 WIRE 288 -96 208 -96 WIRE -192 -64 -192 -96 WIRE 112 16 -192 16 WIRE 256 16 112 16 WIRE 64 48 64 -96 WIRE 112 48 112 16 WIRE 208 48 208 -96 WIRE 256 48 256 16 WIRE 368 48 368 -96 WIRE 416 48 368 48 WIRE 496 48 416 48 WIRE 544 48 496 48 WIRE 496 64 496 48 WIRE 64 128 64 112 WIRE 96 128 64 128 WIRE 208 128 208 112 WIRE 208 128 176 128 WIRE 416 128 416 112 WIRE 544 128 416 128 WIRE 64 144 64 128 WIRE 208 144 208 128 WIRE 64 256 64 208 WIRE 64 256 -144 256 WIRE 208 256 208 208 WIRE 208 256 64 256 WIRE 416 256 416 128 WIRE 416 256 208 256 FLAG 208 -96 Vo FLAG 112 16 Vtrig FLAG -144 256 0 FLAG 416 48 Vc SYMBOL Misc\\SCR 80 112 R180 SYMATTR InstName U1 SYMATTR Value mcr8sn SYMBOL Misc\\SCR 224 112 R180 SYMATTR InstName U2 SYMATTR Value mcr8sn SYMBOL diode 224 208 R180 WINDOW 0 24 72 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName D1 SYMBOL diode 80 208 R180 WINDOW 0 24 72 Left 0 WINDOW 3 24 0 Left 0 SYMATTR InstName D2 SYMBOL voltage 192 128 R90 WINDOW 0 -32 56 VBottom 0 WINDOW 3 32 56 VTop 0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V1 SYMATTR Value SINE(0 50 50) SYMBOL ind 272 -80 R270 WINDOW 0 32 56 VTop 0 WINDOW 3 5 56 VBottom 0 SYMATTR InstName L1 SYMATTR Value 13.5m SYMATTR SpiceLine Rser=0.2 SYMBOL cap 400 48 R0 SYMATTR InstName C1 SYMATTR Value 23500µ SYMATTR SpiceLine Rser=0.032 SYMBOL voltage -192 32 R180 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 SYMATTR InstName V2 SYMATTR Value PULSE(0 10 1m 0 0 1m 10m) SYMBOL res 528 32 R0 SYMATTR InstName R1 SYMATTR Value 10 TEXT 16 264 Left 0 !.tran 0 1 .2 TEXT 488 192 Left 0 !.SUBCKT mcr8sn anode gate cathode PARAMS:\n**************************************\n* Model Generated by CZ LAB *\n* August 27, 2001 *\n* Copyright(c) On Semiconductor *\n* All Rights Reserved *\n*Commercial Use or Resale Restricted *\n**************************************\n*Silicon Controlled Rectifier\n*MODEL FORMAT: PSpice\n+ Vdrm=960v Vrrm=960v Idrm=10u\n+ Ih=0.5ma dVdt=1.5e7\n+ Igt=0.025ma Vgt=0.7v\n* Vgt must be greater than 0.65\n+ Vtm=1.25v Itm=16\n+ Ton=2u Toff=15u\n* Where:\n* Vdrm => Forward breakover voltage\n* Vrrm => Reverse breakdown voltage\n* Idrm => Peak blocking current\n* Ih => Holding current\n* dVdt => Critical value for dV/dt triggering\n* Igt => Gate trigger current\n* Vgt => Gate trigger voltage\n* Vtm => On-state voltage\n* Itm => On-state current\n* Ton => Turn-on time\n* Toff => Turn-off time\n*-------------------------------------------------------------------------------\n* Library of Thyristor (SCR and Triac) models\n* This is a reduced version of MicroSim's Thyristor components library.\n* You are welcome to make as many copies of it as you find convenient.\n* Library of SCR models\n* NOTE: This library requires the "Analog Behavioral Modeling"\n* option available with PSpice. A model developed without\n* Behavioral Modeling was found to be very slow and not\n* very robust.\n* This macromodel uses a controlled switch as the basic SCR\n* structure. In all cases, the designer should use\n* the manufacturer's data book for actual part selection.\n* The required parameters were derived from data sheet (Motorola)\n* information on each part. When available, only "typical"\n* parameters are used (except for Idrm which is always\n* a "max" value). If a "typical" parameter is not available,\n* a "min" or "max" value may be used in which case a comment is\n* made in the library.\n* The SCRs are modeled at room temperature and do not track\n* changes with temperature. Note that Vdrm is specified by the\n* manufacturer as valid over a temperature range. Also, in\n* nearly all cases, dVdt and Toff are specified by the\n* manufacturer at approximately 100 degrees C. This results in a\n* model which is somewhat "conservative" for a room temperature\n* model.\n* The parameter dVdt (when available from the date sheet) is used\n* to model the Critical Rate of Rise of Off-State Voltage. If\n* not specified, dVdt is defaulted to 1000 V/microsecond.\n* A side effect of this model is that the turn-on current, Ion,\n* is determined by Vtm/(Ih*Vdrm). Vtm is also used as the\n* holding voltage.\n* Main conduction path\nScr anode anode0 control 0 Vswitch ; controlled switch\nDak1 anode0 anode2 Dakfwd OFF ; SCR is initially off\nDka cathode anode0 Dkarev OFF\nVIak anode2 cathode ; current sensor\n* dVdt Turn-on\nEmon dvdt0 0 TABLE {v(anode,cathode)} (0 0) (2000 2000)\nCdVdt dvdt0 dvdt1 100pfd ; displacement current\nRdlay dvdt1 dvdt2 1k\nVdVdt dvdt2 cathode DC 0.0\nEdVdt condvdt 0 TABLE {i(vdVdt)-100p*dVdt} (0 0 ) (.1m 10)\nRdVdt condvdt 0 1meg\n* Gate\nRseries gate gate1 {(Vgt-0.65)/Igt}\nRshunt gate1 gate2 {0.65/Igt}\nDgkf gate1 gate2 Dgk\nVIgf gate2 cathode ; current sensor\n* Gate Turn-on\nEgate1 gate4 0 TABLE {i(Vigf)-0.95*Igt} (0 0) (1m 10)\nRgate1 gate4 0 1meg\nEgon1 congate 0 TABLE {v(gate4)*v(anode,cathode)} (0 0) (10 10)\nRgon1 congate 0 1meg\n* Main Turn-on\nEItot Itot 0 TABLE {i(VIak)+5E-5*i(VIgf)/Igt} (0 0) (2000 2000)\nRItot Itot 0 1meg\nEprod prod 0 TABLE {v(anode,cathode)*v(Itot)} (0 0) (1 1)\nRprod prod 0 1meg\nElin conmain 0 TABLE\n+ {10*(v(prod) - (Vtm*Ih))/(Vtm*Ih)} (0 0) (2 10)\nRlin conmain 0 1meg\n* Turn-on/Turn-off control\nEonoff contot 0 TABLE\n+ {v(congate)+v(conmain)+v(condvdt)} (0 0) (10 10)\n* Turn-on/Turn-off delays\nRton contot dlay1 825\nDton dlay1 control Delay\nRtoff contot dlay2 {290*Toff/Ton}\nDtoff control dlay2 Delay\nCton control 0 {Ton/454}\n* Reverse breakdown\nDbreak anode break1 Dbreak\nDbreak2 cathode break1 Dseries\n* Controlled switch model\n.MODEL Vswitch vswitch\n+ (Ron = {(Vtm-0.7)/Itm}, Roff = {Vdrm*Vdrm/(Vtm*Ih)},\n+ Von = 5.0, Voff = 1.5)\n* Diodes\n.MODEL Dgk D (Is=1E-16 Cjo=50pf Rs=5)\n.MODEL Dseries D (Is=1E-14)\n.MODEL Delay D (Is=1E-12 Cjo=5pf Rs=0.01)\n.MODEL Dkarev D (Is=1E-10 Cjo=5pf Rs=0.01)\n.MODEL Dakfwd D (Is=4E-11 Cjo=5pf)\n.MODEL Dbreak D (Ibv=1E-7 Bv={1.1*Vrrm} Cjo=5pf Rs=0.5)\n* Allow the gate to float if required\nRfloat gate cathode 1e10\n.ENDS\n*$